4-Bit Fast Adder Design: Topology and Layout with Self-Resetting Logic for Low Power VLSI Circuits

Dynamic logic families offer good performance over traditional CMOS logic. This is due to the comparatively high noise margins coupled with the ease of implementation. The main drawbacks of dynamic logic circuits are lack of design automation, charge sharing, feedthrough, charge leakage, singleevent upsets, etc. But these draw backs can be eliminated using domino and NORA circuits but still lacks in the application of clock distribution grid and routing to dynamic gates that presents a problem to CAD tools and introduces issues of delay and skew into the circuit design process. A special dynamic logic circuit which resolves these issues is called Self-Resetting Logic (SRL). A new family of self-resetting logic (SRL) primitive gates and adder cells are presented in this paper which can eliminate the above cited issues. The operation of primitive and adder circuit are elucidated and it is simulated using microwind and LT-SPICE simulator. The analysis of basic gates and adder are compared with conventional dynamic logic circuit in terms of area, power dissipation and propagation delays at 0.12-μm 6metal layer CMOS technology is carried out. KeywordsHigh speed, VLSI, Self-resetting logic (SRL), topologies, power dissipation